To reduce the cost and difficulty of chip testing

also improve quality and yield

memory build-in self-test (MBIST) mode and scan chain test mode are included in mass-production chips. As more functions are integrated on a single chip

multiple different clocks are adopted in design. The solution presented  is a physical design method named Mix-mode

which realize normalization of multi-mode based on changing the timing constraints. The method was applied in design of a video processing chip based on 130 nm process and IC Compiler (ICC)  used for placement and routing. The results showed that  the physical layout was better in terms of runtime

timing

power consumption

area and total wire length than that obtained from the Multi-mode method provided by ICC.